In recent years, liquid crystal displays (LCD), characterized by their thinness, light-weightiness, and low power consumption, have been widely used as display devices, and it has become possible to realize a large-screen LCD TV as technologies to enlarge screens and support moving pictures are improved. As the liquid crystal display device, active matrix LCD devices allowing high definition display are currently in use. First, referring to FIG. 21, a typical configuration of an active matrix LCD device will be described. Note that a main structure connected to a pixel of the liquid crystal display unit is schematically shown by an equivalent circuit diagram in FIG. 21.
The display unit (a display panel) 960 of the active matrix LCD device is generally constituted by a semiconductor substrate on which transparent pixel electrodes 964 and thin film transistors (TFT) 963 are disposed in matrix (for instance 1280×3 pixel columns×1024 pixel rows in the case of a color SXGA panel), a counter-substrate having a transparent electrode 966 on the entire surface, and liquid crystal sealed between the two substrates.
The TFTs 963, having a switching function, are on/off controlled by a scanning signal, such that, when the TFTs 963 are turned on, a grayscale (gradation) voltage corresponding to a picture data signal is applied to the pixel electrodes 964 and the transmittance of the liquid crystal is changed by the potential difference between each pixel electrode 964 and the electrode 966 of the counter-substrate. A picture is displayed by having a liquid crystal capacitor 965 maintain this potential difference for a predetermined time.
On the semiconductor substrate, a lattice-like interconnection of data lines 962 that sends a plurality of level voltages (grayscale voltages) applied to each pixel electrode 964 and scanning lines 961 that sends scanning signals are formed (in the case of the aforementioned color SXGA panel, 1280×3 data lines and 1024 scanning lines). The scanning lines 961 and the data lines 962 represent a large capacitive load due to the capacitance generated at the intersections with each other and the capacitance of the liquid crystal interposed between the electrode of the counter-substrate and these lines.
Meanwhile, the scanning signals are supplied from a gate driver 970 to scanning lines 961, and the grayscale voltage is supplied to each pixel electrodes 964 by a data driver 980 via a data line 962. Further, the gate driver 970 and the data driver 980 are controlled by a display controller 950. A clock CLK, control signal, and power supply voltage they need are supplied by the display controller 950, and image data is supplied to the data driver 980. Currently, the image data is mainly digital data.
Data for one frame is rewritten every frame period ( 1/60 second) and is selected in order with each scanning line from one row of pixels to the next (every line). The grayscale voltage is supplied from each data line during the selection period.
Further, it is sufficient for the gate driver 970 to supply at least two-valued scanning signals, while the data driver 980 is required to drive the data lines with grayscale voltages of multi-valued levels corresponding to the number of grayscale levels. Therefore, the data driver 980 comprises a digital-to-analog converter circuit (DAC) composed of a decoder that converts the image data into grayscale voltages and an operation amplifier that amplifies the grayscale voltages and outputs it to the data lines 962.
Further, the recent trend in the liquid crystal display devices is to demand higher picture quality (higher resolution grayscale) and as a result, the voltage amplitudes of the scanning signals and the grayscale signals have a tendency to increase. For this reason, the gate driver 970 and the data driver 980 are demanded to output high voltages. Meanwhile, it is demanded to transfer various control signals and image data signals supplied to the gate driver 970 and the data driver 980 from the display controller 950 at high speed with a small number of wirings and low EMI, and the amplitudes of these signals have a tendency to decrease. Further, even inside the gate driver 970 and the data driver 980, in order to reduce an increase in the area of a logic circuit (an increase in costs) that processes data whose amount also grows as the grayscale resolution increases, a micro process is employed and as a result, the power supply voltage of the logic circuit has a tendency to decrease.
In other words, the gate driver 970 and the data driver 980 are demanded to receive a low voltage and output a high voltage. Therefore, a level shift circuit that converts a low voltage signal at the input into a high voltage signal at the output must convert a low amplitude signal into a high amplitude signal at high speed.
[Non-Patent Document 1]
“Introduction to Super LSI Series 5: Basics of MOS Integrated Circuit),” Kindai Kagaku Sha Co., Ltd., pp. 157-167 (FIG. 5-42).
[Non-Patent Document 2]
Society for Information Display, 2004 International Symposium, Digest of Technical Papers, Volume XXXV, 2004 pp. 1556-1559.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-50-151433
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-A-2-188024
[Patent Document 3]
Japanese Patent Kokai Publication No. JP-A-59-154820